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IP cores

Saturday 5 October 2013, by admin

The current family of ACEN IP cores addresses the arithmetic operations that are not easily designed in a FPGA. The IP cores are based on well-known algorithms fine-tuned to get the most of the structure and resources of the target FPGA . As a consequence the performances and complexity are strongly related to the FPGA vendor and family.
To address high resolution applications the arithmetic operators are declined in two versions:

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